Reza Hashemian
Professor Electrical Engineering
Email: reza@niu.edu
Tel: 815-753-9930
Website: http://www.ceet.niu.edu/faculty/reza/
Education
M.S. (1965), Ph.D. (1968) in Electrical Engineering, University of Wisconsin, Madison Wisc.
Research Interests
- Digital Design with FPGAs
- Analog Circuit Design (Nonlinear DC Biasing)
- Code Compression
- Analog and Digital VLSI
- Computer Arithmetic.
Work Experience
- Faculty at Department of Electrical Engineering, NIU (1987-present)
- MOS modeling/characterization and VLSI design engineer at Signetics Corporation, Sunnyvale, California (1984-1987)
- Department of Electrical Engineering, Sharif University (1968-1984)
- Vice president for research and Industrial cooperation, Sharif University, Tehran, Iran (1983-1984)
- Director of the "Research and Product Center", Iranian Radio and Television Association (1980-1982)
- Associate Director and then Director of the Materials and Energy Research Center (MERC), Sharif University, Tehran, Iran (1974-1979).
Professional Associations and Honors
- Member and then Life Member of IEEE (1965-present)
- Eta Kappa Nu (1965-present)
Selected Publications
- "A Method to Design, Construct and Test Digital Hardware all in Classroom Environment", Proceedings of the FIE2007 Conference, Milwaukee, Wisc., October 11 - 13, 2007.
- "Partial Local Biasing, A New Method to Modify/Tune Amplifiers for a Desirable Performance”, 2007 IEEE International Conference on Electro/Information Technology, IIT, Chicago, May 17 – 19, 2007.
- "Designing Analog Circuits with Reduced Biasing Power", to be published in the Proceedings of the 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France Dec. 10– 13, 2006
- "New Analysis and Design Technique for Analog Circuits ", Proceedings of the 2006 IEEE International Midwest Symposium On Circuits And Systems, San Juan, Puerto Rico, August 6 – 9, 2006.
- "Use of Conditional Additivity in Circuits with Exponential Nonlinearities", Proceedings of the 48th IEEE International Midwest Symposium On Circuits And Systems, Cincinnati, OH, August 7 – 10, 2005.
- " Condensed Table of Huffman Coding, A New Approach to Efficient Coding ", IEEE Trans. on Communications, Vol. 52, no. 1, pp 6 – 8, January 2004.
- "Memory Efficient and High Speed Search Huffman Coding", IEEE Trans. on Communications, IECMBT, vol.43, no.10, pp.2576-2581, October, 1995.
- "Design and Hardware Implementation of a Memory Efficient Huffman Decoding", IEEE Trans. on Consumer Electronics, vo.40, no.3, pp.345-352, August, 1994.
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