Ph.D. (1968), M.S. (1965) in Electrical Engineering, University of Wisconsin, Madison Wisc.
Analog Circuit Design Methodologies, Fixator-Norators, and poles and zeros
Digital Design with FPGAs
Huffman coding and Image compression
Remotely Accessible Laboratories (RLA) for Hardware (FPGAs) Design
Computer Arithmetic for DSP applications
Faculty at the Department of Electrical Engineering, NIU (1987 – Present)
MOS modeling/characterization and VLSI design engineer at Signetics Corporation, Sunnyvale, California (1984-1987)
Department of Electrical Engineering, Sharif University (1968-1984)
Vice president for research and Industrial cooperation, Sharif University, Tehran, Iran (1983-1984)
Director of the "Research and Product Center", Iranian Radio and Television Association (1980-1982)
Associate Director and then Director of the Materials and Energy Research Center (MERC), Sharif University, Tehran, Iran (1974-1979)
Professional Associations and Honors
Member and then Life Member of IEEE (1965-present)
An executive member of the IEEE, Iran Section, 1970 – 72
“Extraction of Poles and Zeros of an RC Circuit with Roots on the Real Axis,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 8, pp. 624-628, August 2014
“Fixator-Norator Pairs vs Direct Analytical Tools in Performing Analog Circuit Designs,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 61, no. 8, pp. 569 - 573, August 2014
“Identification and Extraction of All Real Axis Poles and Zeros in RC and RL Circuits”, IEEE Inter. Conf. on Electro/Information Technology EIT2015, Northern Illinois University, Naperville, IL, May 21 - 23, 2015.
“S-Plane Bode Plots - Identifying Poles and Zeros in a Circuit Transfer Function,”Proceedings of the IEEE LASCAS 2015 Conference, Montevideo, Uruguay, February 24 – 27, 2015
“vLab, A High Speed Multi-Accesses Parallel Processing Remote Laboratory Access for FPGA Design Technology”, Proceeding of the IEEE International Conference on Electro/Information Technology EIT2014, pp 377 – 381, DOI: 10.1109/EIT.2014.6871794, Milwaukee, WI, June 5 - 7, 2014.
"A New Number Method for Conversion of a 2’s Complement to Canonic Signed Digit Number System and its Representation," 30th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, November 3-6, 1996.
"Memory Efficient and High Speed Search Huffman Coding," IEEE Trans. on Communications, IECMBT, vol.43, no.10, pp.2576-2581, October, 1995.
"Design and Hardware Implementation of a Memory Efficient Huffman Decoding", IEEE Trans. on Consumer Electronics, vo.40, no.3, pp.345-352, August, 1994.
"Square Rooting Algorithms for Integer and Floating-Point Numbers," IEEE Transactions on Computers, vol. C 39, no.8, pp. 1025-1029 August 1990.
" Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits ", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, Vol. 20, Issue 12, pp 2220 – 2231, December 2012.
“A Low-Cost Server-Client Methodology for Remote Laboratory Access for Hardware Design” accepted for presentation, FIE2009, San Antonio, Texas, on October 18 – 21, 2009.
" Condensed Table of Huffman Coding, A New Approach to Efficient Coding ", IEEE Trans. on Communications, Vol. 52, no. 1, pp 6 – 8, January 2004.
" Direct Huffman Coding Using Table Of Code Lengths ", IEEE International Conference on Information Technology (ITCC 2003), at Las Vegas, Nevada, April 28 – 30, 2003.
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